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Article

Optimization of Gate-Head-Top/Bottom Lengths of AlGaN/GaN High-Electron-Mobility Transistors with a Gate-Recessed Structure for High-Power Operations: A Simulation Study

1
Division of Electronics and Electrical Engineering, Dongguk University-Seoul, Seoul 04620, Republic of Korea
2
Electronics and Telecommunications Research Institute, Daejeon 34129, Republic of Korea
3
Photonic Components Department, Fraunhofer Heinrich-Hertz Institute, Einsteinufer 37, 10587 Berlin, Germany
*
Author to whom correspondence should be addressed.
Micromachines 2024, 15(1), 57; https://doi.org/10.3390/mi15010057
Submission received: 2 December 2023 / Revised: 22 December 2023 / Accepted: 26 December 2023 / Published: 27 December 2023
(This article belongs to the Special Issue Gallium Nitride-Based Devices, 2nd Edition)

Abstract

:
In this study, we propose an optimized AlGaN/GaN high-electron-mobility transistor (HEMT) with a considerably improved breakdown voltage. First, we matched the simulated data obtained from a basic T-gate HEMT with the measured data obtained from the fabricated device to ensure the reliability of the simulation. Thereafter, to improve the breakdown voltage, we suggested applying a gate-head extended structure. The gate-head-top and gate-head-bottom lengths of the basic T-gate HEMT were symmetrically extended by 0.2 μm steps up to 1.0 μm. The breakdown voltage of the 1.0 μm extended structure was 52% higher than that of the basic T-gate HEMT. However, the cutoff frequency ( f T ) and maximum frequency ( f m a x ) degraded. To minimize the degradation of f T and f m a x , we additionally introduced a gate-recessed structure to the 1.0 μm gate-head extended HEMT. The thickness of the 25 nm AlGaN barrier layer was thinned down to 13 nm in 3 nm steps, and the highest f T and f m a x were obtained at a 6 nm recessed structure. The f T and f m a x of the gate-recessed structure improved by 9% and 28%, respectively, with respect to those of the non-gate-recessed structure, and further improvement of the breakdown voltage by 35% was observed. Consequently, considering the trade-off relationship between the DC and RF characteristics, the 1.0 μm gate-head extended HEMT with the 6 nm gate-recessed structure was found to be the optimized AlGaN/GaN HEMT for high-power operations.

1. Introduction

GaN-based high-electron-mobility transistors (HEMTs), leveraging their superior material properties, such as a wide energy bandgap (3.4 eV) and a high critical electric field (~3.3 MV/cm), have been studied for applications demanding high-power and high-frequency capabilities [1,2,3]. Moreover, a channel layer with a two-dimensional electron gas (2-DEG) is formed in the AlGaN/GaN heterojunction owing to spontaneous and piezoelectric polarization effects [4], which improve the output current density and power amplification characteristics of the device. The AlGaN/GaN HEMTs are widely used in power electronics applications, including high-power and high-frequency operations, owing to these characteristics [5,6,7]. Various field plate (FP) structures in GaN-based HEMTs have been mainly used under high-power conditions. The FP structures redistribute concentrated electric fields at the drain-side gate edge when high voltage is applied, thereby improving the breakdown voltage ( V B D ) [8,9]. Additionally, we symmetrically increased the gate-head-top ( L G a t e - H e a d - T o p ) and gate-head-bottom ( L G a t e - H e a d - B o t t o m ) lengths of the AlGaN/GaN HEMT in this study. Subsequently, we confirmed that V B D improved considerably without the gate-foot length ( L G a t e - F o o t ) of 0.18 μm and the other epitaxial layers changing. Additionally, increases in L G a t e - H e a d - T o p and L G a t e - H e a d - B o t t o m inevitably generated additional parasitic capacitances, which degrade the cut-off frequency ( f T ) and maximum frequency ( f m a x ) characteristics [10,11,12]. Employing the gate-recessed structure can prevent the degradation of frequency characteristics, as it increases transconductance ( g m ) and reduces effective barrier height [13,14,15].
To derive the optimized gate structure, we simulated the DC and RF characteristics by extending L G a t e - H e a d - T o p and L G a t e - H e a d - B o t t o m , and increased the gate-recessed depth of various structures. First, the simulated drain current-gate voltage ( I D S - V G S ) transfer and frequency ( f T and f m a x ) characteristics were matched with the corresponding measured data obtained from a 0.18 μm T-gate AlGaN/GaN HEMTs to ensure the reliability of the results. Subsequently, L G a t e - H e a d - T o p and L G a t e - H e a d - B o t t o m were symmetrically increased up to 1.0 μm, thereby improving the DC characteristics, especially V B D . However, frequency characteristics were inevitably degraded. Therefore, we employed an additional gate-recessed structure to minimize the degradation of f T and f m a x . The gate-recessed structure was applied to the 1.0 μm gate-head extended HEMT, which achieved the largest V B D , and the thickness of the 25 nm AlGaN barrier layer was thinned down to 13 nm by 3 nm steps to form the gate-recessed structure. Consequently, we determined the optimized gate electrode structure that achieves high breakdown voltage and minimizes the degradation of frequency characteristics.

2. Materials and Methods

The top view of the fabricated two-finger transistor of the 0.18 μm T-gate AlGaN/GaN HEMT is displayed in Figure 1a. The contact pads at the left and right centers of the figure act as the gate and drain electrodes, respectively, and two source electrodes are located above and below the drain electrodes.
The red dotted frame in Figure 1a shows the scanning electron microscope image of the unit device consisting of the gate, source, and drain electrodes, and the width of the unit device is 100 μm. Figure 1b depicts the specific dimensions of the unit device of the 0.18 μm T-gate AlGaN/GaN HEMT. The source-to-drain ( L S o u r c e - D r a i n ), gate-to-source ( L G a t e - S o u r c e ), and gate-to-drain ( L G a t e - D r a i n ) lengths of the unit device are 5, 1.05, and 3.15 μm, respectively.
Figure 2a displays a cross-sectional transmission electron microscope image corresponding to the portion in the red dotted frame in Figure 1a. The T-shaped gate electrode consists of three parts, i.e., L G a t e - F o o t , gate-middle length ( L G a t e - M i d d l e ), L G a t e - H e a d - T o p , and L G a t e - H e a d - B o t t o m , which are 0.18, 0.34, 0.6, and 0.8 μm, respectively. A cross-sectional schematic of the basic T-gate structure used in the model is shown in Figure 2b, where S, G, and D stand for the source, gate, and drain. The detailed geometrical parameters of the structure are listed in Table 1.
The AlGaN/GaN heterostructure HEMT was grown on a 4-inch SiC substrate using metal-organic chemical vapor deposition. The epitaxial layers were stacked in the growth sequence in the following order: a nucleation layer with a thickness of 0.2 µm, an Fe-doped GaN buffer layer with a thickness of 2 µm, and an AlGaN barrier layer with a thickness of 25 nm with a nominal Al composition of 25.5%. The Ti/Al/Ni/Au alloyed ohmic contacts required for the source and drain were formed by rapid thermal annealing at 900 °C for 30 s, and device isolation involved P+-ion implantation. Subsequently, a 50 nm SiN layer was deposited on the AlGaN barrier using plasma-enhanced chemical vapor deposition (PECVD). The alloyed ohmic source and drain contacts were interconnected via evaporated Ti/Au metals after etching the SiN layer. The 0.18-μm-width L G a t e - F o o t was first defined via electron beam exposure to a polymethyl methacrylate (PMMA) resist, and the SiN layer beneath the gate pattern was formed via reactive ion etching (RIE). Subsequently, a 0.34 μm wide L G a t e - M i d d l e was formed using additional electron beam exposure after a triple-layer-coating of PMMA/co-polymer/PMMA. The two-step gate-recess to define L G a t e - F o o t and L G a t e - M i d d l e was formed via dry etching using an inductively coupled plasma with a BCl3/Cl2 gas mixture and a wet cleaning process using oxygen plasma treatment, followed by diluted-HCl etching. To form the T-shaped gate electrode, an Ni/Au metal stack with Au and Ni thicknesses of 30 and 500 nm, respectively, was deposited via electron beam evaporation and lifted off. Finally, SiN was deposited via PECVD for device passivation and subsequently etched using RIE to form the ohmic electrode-pad contacts. Further information regarding the fabrication process of the AlGaN/GaN heterostructure HEMT is available in a previous study [16].
Acceptor trap doping was applied in the GaN buffer layer using Fe to improve VBD by minimizing the substrate leakage current and preventing electron-induced punch through [17,18,19]. The peak concentration of acceptor trap doping was 10 18 / c m 3 , which decreased gradually following a Gaussian doping profile [20]. The acceptor doping concentration in the AlGaN/GaN interface region was set to 6.376 × 10 16 / c m 3 based on values reported in a previous study [21].
The conduction band energy level of a basic T-gate structure was simulated as a function of depth. When AlGaN and GaN come in contact, the top and bottom of the AlGaN layer is negatively and positively charged, respectively, due to the polarization effect occurring in the AlGaN/GaN interfaces. Owing to polarization charges at the top and bottom of the AlGaN layer, an electric field is generated, and energy band bending is induced toward the AlGaN/GaN interface. The electric field causes the electrons in the conduction band of the AlGaN layer to move toward the positively charged AlGaN/GaN interface and accumulate. Subsequently, the accumulated electrons in the AlGaN layer flow into the GaN layer and become confined until the Fermi levels of AlGaN and GaN become equal, thereby forming the 2-DEG. Therefore, the 2-DEG with a density of 5.67 × 10 12 / c m 2 is formed in the heterojunction interface between AlGaN and GaN [21].
To ensure the reliability of the simulation, appropriate parameters and models must be applied for each material. Because the heat generated during device operation degrades the device performance, the self-heating effect (SHE) must be considered. The equation of the thermal conductivity model can be expressed as follows:
k T L = ( T C . C O N S T ) / T L 300 T C . N P O W ,
where T L is the local lattice temperature, TC.CONST is the thermal conductivity constants of the material at 300 K, and TC.NPOW is the thermal conductivity factor, which represents the temperature-dependent thermal conductivity, respectively [22,23]. Based on the calculated thermal conductivity model, the lattice heat flow model is given by:
C T L t = k T L + H ,
where C, T L , and k are the heat capacitance per unit volume, local lattice temperature, and thermal conductivity, respectively [24,25,26], and H is the generated heat, which can be expressed as follows:
H = ( J n + J p ) · E ,
where J n , J p , and E are the electron current density, hole current density, and electric field, respectively [27]. By considering Equations (1)–(3), the SHE can be applied to the simulation by setting proper values for each parameter [28]. In addition, GANSAT and FMCT electron-mobility models, Shockley–Read–Hall recombination, Auger recombination, Selberherr’s models, and the Fermi–Dirac distribution function were considered in the simulation for all layers [29,30]. The values of specific parameters applied to the simulation are listed in Table 2 [31,32].
We analyzed the frequency characteristics to prevent the deterioration of RF characteristics when the gate-head structure is changed. Current gain and unilateral power gain were used to calculate f T and f m a x , respectively. f T can be expressed as follows:
f T = g m 2 π ( C g s + C g d ) g m 2 π C g s ,
where g m is the transconductance, and C g s and C g d are the gate-to-source and gate-to-drain capacitances, respectively. Parasitic capacitances such as C g s and C g d have an inverse relationship with fT, as per Equation (4). Therefore, C g s and C g d must be decreased to increase f T . We can also determine f m a x by applying the calculated value of f T , and f m a x can be expressed as:
f m a x = f T 2 π f T C g d R s + R g + R g s + 2 π L s + G d s ( R s + R g + R g s + π f T L s ) f T 8 π R g C g d ,
where R s , R g , and R g s are the source, gate, and gate-to-source resistances, respectively; L s is the source inductance; and G d s is the output conductance. Equations (4) and (5) can be used to confirm that C g s and C g d are crucial for determining the values of f T and f m a x , and capacitance can be expressed as:
C = ε A d ,
where ε , A , and d are the permittivity of the dielectric constant, the area of the plate overlaps in square meters, and the distance between plates in meters, respectively. The distance between the electrodes can be increased, the area of the electrode can be reduced, or a low dielectric constant material used for passivation can reduce capacitance.

3. Results

3.1. Matching the Measured and Simulated Data Obtained from the Basic T-Gate HEMT

In this study, we first matched the measured and simulated data obtained from an actual fabricated basic T-gate HEMT to ensure the reliability of the simulation. The simulated drain current–gate voltage ( I D S V G S ) transfer characteristics, f T , and f m a x were matched with the corresponding measured values. Figure 3a shows the overlapping values of the measured and simulated I D S V G S transfer characteristics at a drain voltage ( V D S ) of 10 V and gate voltage ( V G S ) in the range of −6–0 V. The DC characteristics of the actual fabricated device were measured using an HP4142B modular DC source/monitor probe station (Keysight, Santa Rosa, CA, USA) and a Summit 12000 probe station (Cascade Microtech, Beaverton, OR, USA). The measured and simulated threshold voltages ( V t h ) were equal, i.e., −4.3 V, and the measured and simulated maximum transconductances ( G m ) were 282.75 and 278.97 mS/mm, respectively, which were well-matched with a 1.35% error rate. At a V G S of 0 V, the measured and simulated drain currents ( I d s s ) were 873.40 and 873.46 mA/mm, respectively, which were also well-matched with only an error rate of 0.006%.
Figure 3b shows the measured and simulated f T and f m a x at V G S of −3 V and V D S of 10 V. The small-signal RF performance of the fabricated basic T-gate HEMT was measured using a PNA-X N5245A network analyzer (Keysight, Santa Rosa, CA, USA) in the frequency range of 0.5–50 GHz. Furthermore, f T was extracted by extrapolating the current gain ( H 21 ) to 0 dB using a −20 dB/decade slope, and fmax was obtained from the extrapolation of the maximum stable gain/maximum available gain to unity using the same slope [33]. The measured and simulated f T of the basic T-gate HEMT were 43.34 GHz and 45.08 GHz, and f m a x were 109.51 GHz and 114.29 GHz, respectively. The measured and simulated values of f T and f m a x were confirmed to be well-matched with the error rates of 4.01% and 4.36%, respectively.

3.2. Comparative Analysis of Basic T-Gate and Gate-Head Extended HEMTs

To improve the V B D characteristics, we varied the gate-head extended length. We increased L G a t e - H e a d - T o p and L G a t e - H e a d - B o t t o m of the basic T-gate HEMT, which were originally 0.6 and 0.8 μm, respectively. Additionally, L G a t e - H e a d - T o p and L G a t e - H e a d - B o t t o m were symmetrically extended in 0.2 μm steps up to 1.0 μm, as shown in Figure 4.
A gate-head extended HEMT was modeled by increasing L G a t e - H e a d - T o p and L G a t e - H e a d - B o t t o m symmetrically until the sidewall passivation of the source electrode and the gate electrode contacted. Except for L G a t e - H e a d - T o p and L G a t e - H e a d - B o t t o m , all the remaining geometrical parameters of the device were maintained. The initial values of L G a t e - F o o t and L G a t e - M i d d l e were 0.18 and 0.34 μm, respectively. The structures were named as 0.2 μm extended, 0.4 μm extended, 0.6 μm extended, 0.8 μm extended, and 1.0 μm extended HEMTs, according to the extended lengths of the gate-head. Figure 5 explains the schematics of a basic T-gate and gate-head extended HEMT.

3.2.1. Simulation of the DC Characteristics

We simulated and analyzed the DC characteristics of basic T-gate and gate-head extended HEMTs. Figure 5a,b show the I D S V G S transfer characteristics simulated at V D S values of 10 and 20 V, respectively. Additionally, L G a t e - H e a d - T o p and L G a t e - H e a d - B o t t o m increased, and I d s s and G m increased slightly. However, almost no significant changes are observed, and V t h remains constant at −4.3 V, as shown in Figure 5a.
Figure 5b confirms that drain currents and g m values simulated at a V D S of 20 V were smaller than those obtained at a V D S of 10 V because the generated SHE was more at a higher V D S . As shown in Figure 5c, the I D S V D S transfer characteristics were simulated at V G S values of −5, −4, −3, −2, −1, and 0 V. As the drain voltage increases, the drain current decreases owing to the increase in heat generation and electron scattering.
Figure 6a shows the electric field distributions in the 2-DEG channel layer of the basic T-gate and gate-head extended HEMTs. The electric fields of the gate-head extended HEMT were redistributed, thereby reducing the peak electric field. Generally, impact ionization can be avoided by reducing the concentrated electric fields at the drain-side gate edge. Additionally, improving the V B D characteristics can be a possible solution for preventing severe impact ionization [34]. Furthermore, V B D was simulated at a gate voltage of −7 V to completely turn off the channel, and V B D was determined under a drain leakage current of 1 mA/mm. As shown in Figure 6b, the basic T-gate HEMT has a V B D of 167.78 V, and the 0.2, 0.4, 0.6, 0.8, and 1.0 μm extended HEMTs have V B D values of 181.50, 199.45, 218.46, 239.03, and 255.11 V, respectively. The maximum V B D , which is 52.05% higher than that of a basic T-gate HEMT, was obtained from the 1.0 μm extended HEMT.

3.2.2. Simulation of RF Characteristics

As shown in Figure 7, C g s and C g d of the basic T-gate and gate-head extended HEMTs at a V D S of 10 V and a V G S of −3 V are compared. The increase in L G a t e - H e a d - T o p and L G a t e - H e a d - B o t t o m resulted in increases in C g s and C g d .
The relationship between capacitance and distance is expressed in Equation (6). Additionally, C g s is confirmed to typically be higher than C g d because L g s is shorter than L g d , as shown in Table 1. In Figure 7a,b, we observe that the highest C g s and C g d are obtained in the 1.0 μm extended structure, because L g s and L g d were reduced as the gate-head extended structure was applied.
Figure 8 depicts the simulated f T and f m a x obtained using the basic T-gate and gate-head extended HEMTs, which were simulated at a V D S of 10 V and a V G S of −3 V. The simulated f T of the basic T-gate HEMT was 45.08 GHz, and those of the 0.2, 0.4, 0.6, 0.8, and 1.0 μm extended HEMTs were 42.69, 40.35, 38.28, 36.38, and 34.53 GHz, respectively. Furthermore, f T tended to decrease as L G a t e - H e a d - T o p and L G a t e - H e a d - B o t t o m increased with the increase in C g s .
The f m a x value of the basic T-gate HEMT was 114.29 GHz, and those of the 0.2, 0.4, 0.6, 0.8, and 1.0 μm extended HEMTs were 107.72, 102.37, 92.71, 88.71, and 81.81 GHz, respectively. According to Equation (5), the f m a x of the gate-head extended HEMTs decreased because f m a x is a function of C g d and f T . Consequently, we observed that f T and f m a x considerably deteriorated by 30.55% and 39.70%, respectively, as the gate-extended HEMTs were applied.

3.3. Employment of a Gate-Recessed Structure in the 1.0 μm Extended HEMT

We confirmed that the 1.0 μm extended HEMT exhibits the highest V B D . However, it had the lowest f T and f m a x among the gate-head extended HEMTs.
We applied a gate-recessed structure to the 1.0 μm extended HEMT to further improve V B D and prevent the deterioration of frequency characteristics such as f T and f m a x . Figure 9 shows the schematic of the 1.0 μm extended HEMT and 1.0 μm extended HEMT with the gate-recessed structure. The thickness of the 25 nm-thick AlGaN barrier layer was reduced to 13 nm in 3 nm steps to form the gate-recessed structure. Except for the gate-recessed depth, all the remaining geometrical parameters of the device were fixed. Subsequently, we simulated and analyzed the operational characteristics of the gate-recessed structures to determine the optimum gate-recessed depth.

3.3.1. Simulation of DC Characteristics

First, we simulated the DC characteristics, such as I D S V G S transfer characteristics, 2-DEG density, and V B D , by increasing the gate-recessed depth. Figure 10a,b show the I D S V G S transfer characteristics simulated at V D S values of 10 and 20 V, respectively. The G m of the gate-recessed structure increased as the distance between the gate electrode and channel decreased [35]. According to Equation (7), V t h shifted positively as the thickness of the AlGaN barrier under the gate electrode decreased [36].
V t h e f f b E C q N S d A l G a N 2 2 · ε A l G a N σ d A l G a N ε A l G a N ,
where e f f b denotes the barrier height of the Schottky contact, E C is the discontinuity of the conduction band, q is the electron charge, N S is the 2-DEG concentration, and σ is the polarization charge density. The parameters associated with AlGaN are d A l G a N and ε A l G a N , indicating the thickness and permittivity of the AlGaN, respectively.
As shown in Figure 10a, the V t h of the 0, 3, 6, 9, and 12 nm recessed structures were −4.3, −3.7, −3.1, −2.5, and −1.9 V, respectively, and the simulated values of G m were 276.89, 344.91, 353.99, 370.06, and 389.84 mS/mm, respectively. The G m of the 12 nm recessed structure improved by 40.79% with respect to that of the non-gate-recessed structure. In Figure 10b, when a V D S of 20 V is applied, the severe SHE affects the reduction of the drain current. Additionally, V t h and G m were confirmed to exhibit similar tendencies to those of the corresponding simulated parameters at a drain voltage of 10 V.
Figure 11 shows the simulated 2-DEG densities of the five different gate-recessed structures simulated under the zero-bias condition. The 2-DEG density was observed to decrease as the gate-recessed depth increased; the 2-DEG density as a function of AlGaN barrier thickness was consistent with the theoretical calculation reported in previous studies [37,38,39].
Figure 12a shows the electric field distributions in the 2-DEG channel layer of the 0, 3, 6, 9, and 12 nm recessed structures. Considering the V t h shift, the electric fields of the structures were simulated at V G S values of −7, −6.4, −5.8, −5.2, and −4.6 V. The gate-recessed structure can redistribute the electric fields that are concentrated at a drain-side gate edge, unlike the non-gate-recessed structure. However, when the results obtained from the 3, 6, 9, and 12 nm recessed structures were compared, no significant changes were found in the electric field distributions. Figure 12b shows the V B D values of the five different gate-recessed structures simulated at a pinch-off. The V B D values of the 0, 3, 6, 9, and 12 nm recessed structures were 255.11, 342.03, 346.83, 350.33, and 351.85 V, respectively. The decrease in the electric field increased V B D . Additionally, the recessed gate electrode in the AlGaN barrier results in close proximity between the gate and the channel, which improves carrier density. This increased carrier density generates a large depletion region around the gate and can increase the breakdown voltage due to the existence of a high potential barrier that helps prevent impact ionization. The largest V B D was observed in a 12 nm recessed structure, which was improved by 37.92% with respect to that of the non-gate-recessed structure.

3.3.2. Simulation of the RF Characteristics

The RF characteristics were simulated to identify the optimized gate-recessed depth, aiming to improve the frequency characteristics, such as f T and f m a x . Additionally, C g s and C g d were simulated at a V D S of 10 V. Considering the positive shift of V t h , different V G S values of −3.0, −2.4, −1.8, −1.2, and −0.6 V were applied when simulating the 0, 3, 6, 9, and 12 nm recessed structures, respectively. As shown in Figure 13, the gate-recessed depth, C g s , and C g d increased.
Furthermore, f T and f m a x are simulated as shown in Figure 14, and the same V G S and V D S as those mentioned above are applied. Both f T and f m a x of the gate-recessed structures were higher than that of the non-gate-recessed structures. Furthermore, as the recessed depth increased, f T and f m a x increased up to a certain depth. However, beyond that depth, both f T and f m a x started to decrease. The largest f T and f m a x values of 37.58 and 104.91 GHz were obtained in the 6 nm recessed structure, and these values were improved by 8.83% and 28.24%, respectively, with respect to those of the non-gate-recessed structure. These results were directly affected by the increased value of g m owing to the decrease in the distance between the gate electrode and the channel. Ideally, the increase in C g s , C g d , and g m compensated for each other, resulting in constant values of f T ; increases in C g s and C g d of the active gate region decrease the influence of parasitic capacitance components. Therefore, g m has a dominant effect in determining the value of f T . However, at a certain point, when the rate of increase of g m reduces progressively, g m is no longer a major factor in determining f T and f m a x . Thus, frequency characteristics such as f T and f m a x can be improved by applying a gate-recessed structure [13,40]. Consequently, we suggest that the 6 nm recessed structure is the optimized one, considering high V B D and remarkable f T and f m a x .

4. Discussion

In this study, we simulated and analyzed the DC and RF characteristics of 0.18 μm T-gate AlGaN/GaN HEMTs by symmetrically increasing L G a t e - H e a d - T o p and L G a t e - H e a d - B o t t o m . We confirmed the trade-off relationship between V B D and frequency characteristics. The 1.0 μm gate-head extended HEMT exhibited a remarkable V B D , but the frequency characteristics, such as f T and f m a x , were severely deteriorated. Unlike that of the basic T-gate structure, the V B D of the gate-head extended structure increased by 52.05%, whereas f T and f m a x decreased by 30.55% and 39.70%, respectively.
Therefore, the gate-recessed structure was applied to the 1.0 μm extended HEMT to minimize the degradation of frequency characteristics. The gate-recessed depth of the 6 nm structure demonstrated the lowest f T and f m a x degradation, with further improvement in V B D . Consequently, V B D improved by 106.72% with respect to that of the basic T-gate HEMT, whereas f T and f m a x were only reduced by 19.96% and 8.94%, respectively. The proposed AlGaN/GaN HEMT structure shows a notable enhancement in V B D [41].

5. Conclusions

This paper presents a simulation study on 0.18 μm T-gate AlGaN/GaN HEMTs, in which the gate-head lengths are increased, and a gate-recessed structure is employed. To propose the optimized gate-head structure, I–V transfer curves, capacitances, and frequency characteristics were simulated. Before simulating the various HEMT structures, all simulation parameters were precisely set by matching with the measured data obtained from the fabricated HEMT to ascertain the reliability of the simulated results. Finally, we propose a 1.0 μm extended HEMT with a 6 nm gate-recessed structure as the optimized device by considering the trade-off relationship between V B D and the frequency characteristics. The optimized device demonstrated a significant improvement in V B D and an acceptable degradation of frequency characteristics with respect to the basic T-gate structure. Consequently, the simulation results prove that the proposed structure is a promising candidate for high-power applications.

Author Contributions

Conceptualization and writing original draft preparation, W.-S.K.; software (SILVACO DeckBuild (version 5.2.8.R) and Tonyplot (version 3.10.24.R)) and investigation, J.-H.C.; formal analysis and data curation, D.K.; validation and formal analysis, J.-H.K.; formal analysis and investigation, J.-H.L.; validation and formal analysis, B.-G.M.; validation and investigation, D.M.K.; resources and investigation, J.H.C.; supervision, funding acquisition, resources, and writing—review and editing, H.-S.K. All authors have read and agreed to the published version of the manuscript.

Funding

This work was partly supported by Institute of Information and Communications Technology Planning and Evaluation (IITP) grant funded by the Korean government (MSIT) (No. 2021-0-00760, the Development of GaN-based process technology and RF components for 28 GHz 5G base stations) and the Korea Institute for Advancement of Technology (KIAT) grant funded by the Korean government (MOTIE) (No. P0017307, Fostering Global Talents for Innovative Growth Program).

Data Availability Statement

Data are contained within the article.

Conflicts of Interest

The authors declare no conflicts of interest.

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Figure 1. Scanning electron microscope image of the fabricated 0.18 μm T-gate AlGaN/GaN high-electron-mobility transistor structure: (a) A top view of the two-finger transistor device. The red dotted frame shows the unit device. (b) A top view of the unit device with specific dimensions.
Figure 1. Scanning electron microscope image of the fabricated 0.18 μm T-gate AlGaN/GaN high-electron-mobility transistor structure: (a) A top view of the two-finger transistor device. The red dotted frame shows the unit device. (b) A top view of the unit device with specific dimensions.
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Figure 2. 0.18 μm T-gate AlGaN/GaN high-electron-mobility transistor structure: (a) a cross-sectional transmission electron microscope image of the gate electrode and (b) a cross-sectional schematic illustration of the unit device structure used for modelling.
Figure 2. 0.18 μm T-gate AlGaN/GaN high-electron-mobility transistor structure: (a) a cross-sectional transmission electron microscope image of the gate electrode and (b) a cross-sectional schematic illustration of the unit device structure used for modelling.
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Figure 3. Comparison between the measured and simulated results: (a) drain current-gate voltage ( I D S - V G S ) transfer characteristics, (b) cut-off frequency, and maximum frequency of a basic T-gate HEMT at a drain voltage ( V D S ) = 10 V and a gate voltage ( V G S ) = −3 V.
Figure 3. Comparison between the measured and simulated results: (a) drain current-gate voltage ( I D S - V G S ) transfer characteristics, (b) cut-off frequency, and maximum frequency of a basic T-gate HEMT at a drain voltage ( V D S ) = 10 V and a gate voltage ( V G S ) = −3 V.
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Figure 4. Schematics of the gate electrode structures of the 0.18 μm T-gate AlGaN/GaN HEMT: (a) basic T-gate HEMT and (b) gate-head extended HEMT, where the white dashed lines represent the initial size of gate-head before extension.
Figure 4. Schematics of the gate electrode structures of the 0.18 μm T-gate AlGaN/GaN HEMT: (a) basic T-gate HEMT and (b) gate-head extended HEMT, where the white dashed lines represent the initial size of gate-head before extension.
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Figure 5. Simulation of the DC characteristics of the gate-head length extended structures: I D S - V G S transfer characteristics at (a) V D S = 10 V and (b) V D S = 20 V and (c) drain current-drain voltage ( I D S - V D S ) output characteristics at gate voltages of −5, −4, −3, −2, −1, and 0 V.
Figure 5. Simulation of the DC characteristics of the gate-head length extended structures: I D S - V G S transfer characteristics at (a) V D S = 10 V and (b) V D S = 20 V and (c) drain current-drain voltage ( I D S - V D S ) output characteristics at gate voltages of −5, −4, −3, −2, −1, and 0 V.
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Figure 6. Simulations using different gate-head extended structures: (a) electric field distributions across the two-dimensional electron gas channel layer between the source and drain electrodes at VGS = −7 V and VDS = 50 V and (b) breakdown voltage characteristics at VGS = −7 V.
Figure 6. Simulations using different gate-head extended structures: (a) electric field distributions across the two-dimensional electron gas channel layer between the source and drain electrodes at VGS = −7 V and VDS = 50 V and (b) breakdown voltage characteristics at VGS = −7 V.
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Figure 7. Capacitance characteristics as a function of frequency for different gate extended structures: (a) gate-to-source capacitances and (b) gate-to-drain capacitances.
Figure 7. Capacitance characteristics as a function of frequency for different gate extended structures: (a) gate-to-source capacitances and (b) gate-to-drain capacitances.
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Figure 8. Simulated frequency values of the gate-head extended HEMTs at V D S = 10 V and V G S = −3 V: (a) f T and (b) f m a x .
Figure 8. Simulated frequency values of the gate-head extended HEMTs at V D S = 10 V and V G S = −3 V: (a) f T and (b) f m a x .
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Figure 9. Cross-section schematics of the 1.0 μm extended HEMT: (a) non-gate-recessed structure and (b) gate-recessed structure.
Figure 9. Cross-section schematics of the 1.0 μm extended HEMT: (a) non-gate-recessed structure and (b) gate-recessed structure.
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Figure 10. Simulated DC characteristics with gate-recessed depths between 0 to 12 nm: I D S V G S transfer characteristics at (a) V D S = 10 V; and (b) V D S = 20 V.
Figure 10. Simulated DC characteristics with gate-recessed depths between 0 to 12 nm: I D S V G S transfer characteristics at (a) V D S = 10 V; and (b) V D S = 20 V.
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Figure 11. Simulated 2-DEG density as a function of gate-recessed depth.
Figure 11. Simulated 2-DEG density as a function of gate-recessed depth.
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Figure 12. (a) Electric field distributions in the 2-DEG channel layer between the source and drain electrodes at V D S = 50 V under the pinch-off condition. The inset figure displays electric filed distributions between 2.825 to 3.025 μm and (b) off-state breakdown characteristics.
Figure 12. (a) Electric field distributions in the 2-DEG channel layer between the source and drain electrodes at V D S = 50 V under the pinch-off condition. The inset figure displays electric filed distributions between 2.825 to 3.025 μm and (b) off-state breakdown characteristics.
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Figure 13. Capacitance characteristics as a function of frequency for different gate-recessed structures: (a) gate-to-source capacitances and (b) gate-to-drain capacitances.
Figure 13. Capacitance characteristics as a function of frequency for different gate-recessed structures: (a) gate-to-source capacitances and (b) gate-to-drain capacitances.
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Figure 14. Simulated values of non-gate-recessed and gate-recessed structures: (a) f T ; (b) f m a x .
Figure 14. Simulated values of non-gate-recessed and gate-recessed structures: (a) f T ; (b) f m a x .
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Table 1. Geometrical parameters of the 0.18 μm T-gate AlGaN/GaN HEMT.
Table 1. Geometrical parameters of the 0.18 μm T-gate AlGaN/GaN HEMT.
ParameterValue (μm)
L S o u r c e - D r a i n 5
L G a t e - S o u r c e 1.05
L G a t e - D r a i n 3.15
L G a t e - F o o t 0.18
L G a t e - M i d d l e 0.34
L G a t e - H e a d - B o t t o m 0.8
L G a t e - H e a d - T o p 0.6
L S i d e w a l l 0.2
Nucleation layer0.2
GaN buffer2
AlGaN barrier0.025
1st passivation0.05
2nd passivation0.25
Table 2. Material parameters at room temperature applied in the simulation.
Table 2. Material parameters at room temperature applied in the simulation.
ParametersUnitsGaNAlGaN
Bandgap energyeV3.393.88
Electron affinityeV4.22.3
Relative permittivity-9.59.38
Low field electron mobilitycm2/V-s1500300
High field electron mobility-GANSAT mobility model
Saturation velocitycm/s 1.91 × 10 7 1.12 × 10 7
Shockley-Read-Hall lifetimes 5.67 × 10 12 5.67 × 10 12
Thermal conductivity constantW/cm-K1.30.4
Thermal conductivity factor-0.430
Acceptor trap doping/ c m 3 10 18 -
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Kang, W.-S.; Choi, J.-H.; Kim, D.; Kim, J.-H.; Lee, J.-H.; Min, B.-G.; Kang, D.M.; Choi, J.H.; Kim, H.-S. Optimization of Gate-Head-Top/Bottom Lengths of AlGaN/GaN High-Electron-Mobility Transistors with a Gate-Recessed Structure for High-Power Operations: A Simulation Study. Micromachines 2024, 15, 57. https://doi.org/10.3390/mi15010057

AMA Style

Kang W-S, Choi J-H, Kim D, Kim J-H, Lee J-H, Min B-G, Kang DM, Choi JH, Kim H-S. Optimization of Gate-Head-Top/Bottom Lengths of AlGaN/GaN High-Electron-Mobility Transistors with a Gate-Recessed Structure for High-Power Operations: A Simulation Study. Micromachines. 2024; 15(1):57. https://doi.org/10.3390/mi15010057

Chicago/Turabian Style

Kang, Woo-Seok, Jun-Hyeok Choi, Dohyung Kim, Ji-Hun Kim, Jun-Ho Lee, Byoung-Gue Min, Dong Min Kang, Jung Han Choi, and Hyun-Seok Kim. 2024. "Optimization of Gate-Head-Top/Bottom Lengths of AlGaN/GaN High-Electron-Mobility Transistors with a Gate-Recessed Structure for High-Power Operations: A Simulation Study" Micromachines 15, no. 1: 57. https://doi.org/10.3390/mi15010057

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